The present invention relates to DRAM device ideal for preventing soft errors.
So-called soft errors (information inversions) in memories such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memories) are broadly grouped into a mode occurring due to fluctuations in voltage potential from carriers generated during ray (ion) bombardment that collect in the node diffusion layer; and a mode occurring when a parasitic bipolar element formed over the two diffusion layers and substrate of a transistor configuring a memory cell operates (turns on) causing fluctuations in the voltage potential of the node diffusion layer. So in recent years, greater immunity to soft errors is needed that makes (parasitic) operation of a parasitic bipolar element formed over the two diffusion layers and substrate of a transistor less likely to occur.
The DRAM will however have a small SER (Soft Error Rate) per bit unit compared to the SRAM provided that the two devices have the same cell voltage and design standards. One reason for this small SER is that the DRAM has a smaller surface area on the memory node side diffusion layer (node diffusion layer) compared to the SRAM and so the electrical charge accumulated during ray (ion) bombardment is small. Another reason is the large electrical charge quantity accumulated in nodes having a capacitor (capacitance element). This small SER has up to now been the reason for the lack of intense efforts to find countermeasures to soft errors.
However, the DRAM has a small memory cell size compared to the SRAM and therefore possesses a large memory capacity per single chip. So in a DRAM the soft error rate (SER) per single chip is more of a problem than the SER per bit unit. The high degree of integration in semiconductor circuits as well as ever larger capacity devices have served to aggravate this problem still further.
Suppressing the operation of the above stated parasitic bipolar element requires lowering the resistance value of the substrate or wells (hereafter collectively called, well) forming the transistor configuring the memory cell, that is known for example as a latch-up countermeasure.
Japanese Unexamined Patent Application Publication No. Hei6(1994)-20469 and Japanese Unexamined Patent Application Publication No. 2003-100904 disclose related technology.
Japanese Unexamined Patent Application Publication No. Hei6(1994)-20469 discloses a memory device to temporarily apply a specified voltage potential to the array well in order to reduce the well noise.
Japanese Unexamined Patent Application Publication No. 2003-100904 discloses a semiconductor integrated circuit device containing a SRAM forming the embedded impurity layer for a countermeasure to alpha (α) ray soft errors.